This invention relates generally to packaging techniques for integrated circuits and, more particularly, to a package for a semiconductor wafer which permits the wafer to be used in conjunction with a printed circuit board.
Wafer scale integration implies the ability to create an integrated circuit which is large enough to cover the entire surface of a silicon wafer (typically having a diameter of approximately three inches). Instead of being diced into chips, as wafers are for large scale integrated circuits, the wafers are utilized whole or with very marginal trimming. The successful implementation of wafer scale integration requires more than a simple extension of current technology. Specific problems facing Design and System Engineers include, among other things, heat dissipation and packaging.
Until now, wafer scale integration has been utilized only in conjunction with large main frame equipment where weight and space considerations are not critical by companies such as IBM and Trilogy. Not only are the packaging modules associated with main frame uses complex, bulky, and expensive, but they also do not adequately protect the wafer from unwanted shocks, vibrations and other mechanical stresses.